Own SoC and block-level DFT planning, DFT circuit design, test patterns, timing constraints, and bring-up support.
Responsibilities
- Develop competitive SoC and block-level DFT strategies to improve coverage, optimize test circuitry, reduce test cost, and lower test power.
- Implement DFT circuitry including Scan, MBIST, BScan, and test circuits for analog IP.
- Create DFT-mode timing constraints and support DFT timing closure.
- Design and verify high-coverage DFT test patterns and functional patterns.
- Support hardware bring-up debugging and ATE bring-up.
Requirements
- Bachelor's degree or above in electronics or a related field, with 5+ years of DFT experience and ownership of DFT for at least one successful large SoC project.
- Strong knowledge of DFT structures including Scan, MBIST, and BScan.
- Hands-on experience with mainstream DFT design tools.
- Solid digital circuit fundamentals, strong ASIC design and verification skills, RTL and gate-level debug capability, and rich Formal and STA experience.
- Proficiency with scripting languages such as Perl, Python, Tcl, and Shell.
Nice to have
- Experience integrating test solutions for common IP such as Ethernet, PCIe, PLL, and TVSensor.