Lead subsystem or full-system verification architecture and drive complex-module verification and coverage closure.
Responsibilities
- Build and develop UVM verification environments.
- Develop test cases and debug simulations.
- Run regression testing and drive coverage closure.
Requirements
- Bachelor's degree or above in electronics or a related field.
- 6+ years of relevant experience.
- Deep UVM methodology expertise and ability to lead subsystem or full-system verification architecture design.
- Strong hands-on experience with simulation and verification tools.
- Deep knowledge of bus protocols and verification experience with complex interfaces or other complex modules.