Open Role

Silicon Verification Engineer

Build UVM environments, develop test cases, debug simulations, run regressions, and close coverage.

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Build UVM environments, develop test cases, debug simulations, run regressions, and close coverage.

Responsibilities

  • Build and develop UVM verification environments.
  • Develop test cases and debug simulations.
  • Run regression testing and drive coverage closure.

Requirements

  • Bachelor's degree or above in electronics or a related field.
  • 2+ years of relevant experience.
  • Strong SystemVerilog skills, solid UVM methodology experience, and hands-on experience with simulation and verification tools.
  • Strong knowledge of one or two core bus protocols.
  • Ability to independently build and complete module-level verification.